The semiconductor integrated circuit (IC) industry has experienced rapid growth in recent years. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
Bond pad (or bonding pad) structures have been used to establish electrical connections between components on an IC chip and external devices. Traditionally, each bond pad has an area reserved for the formation of a bonding ball or bump, as well as a separate area reserved for probe testing. An interconnect structure is formed below the bond pad structure. However, as IC device sizes continue to shrink, the region of the interconnect structure under the area reserved for probe testing is typically too small to be used for circuit routing. This results in wasted space within the interconnect structure, and consequently reduces the efficiency of the IC and increases fabrication costs.
Therefore, while existing methods of fabricating bond pad structures for semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.